SX18 영상(NTSC) 동기검출
Untested SX code for detecting video sync with the onboard comparator
Nikolai Golovchenko says:
Sync detection is sure possible with a SX. I made a quick test on the evaluation board (50 MHz SX28),
just for horizontal sync, using the comparator to catch the sync pulses.
It works in most cases, but sometimes, when video is bad quality (noisy, but screen is stable) lines
are missed with that setup. There are a few problems:
1) Comparator lowest input voltage level is 0.4V. With a 0 to 1V video,
sync threshold is at about 0.15V. So it is out of specs, though seems to be working.
2) Noise. I wonder how screen remains stable even when signal is noisy.
There must be some filtering in a TV. I'll try to dig the sync separator circuit from an old TV.
3) SX counts the pulse width in a loop like:
mov w, #5
mov dx, w
mov w, #128-100
mov RTCC, w
mov w, #compMode
mov !RB, w
mov temp, w
sb RTCC.7 ;or any other reg my be used for
;too long - repeat pulse catch
The inner loop takes 8 cycles (without comparator that would be 6 cycles).
So the comparator is sampled every 8 cycles, and maximum jitter in sync detection is 8 cycles.
That can be visible if SX frequency is too low.
Probably, it will be better to build an external circuit on a transistor and not use the comparator altogether.
Nikolai Golovchenko says:
Okay, synchronizing to horizontal pulses video in software works now.
The trickiest part was to lock to sync pulses with the free running internal oscillator.
Even the smallest errors (under 0.01 us per line) build up very quickly and synchronization fails...
The program implements only horizontal sync locking,
but vertical sync pulses detection should be a bit easier since they coincide
with horizontal ones. Here is the details:
I used the built-in comparator and a DC level shifter to separate sync pulses.
Here is the circuit in ascii 'art'.
The resistors R2,R3 and diode VD1 set about a 60 mV threshold
above the sync pulses lower level (sync pulses are negative going).
Surprisingly, the comparator negative input reference should have been taken *above*
the transistor base (as it is in the circuit).
One would assume that BE voltage drop is about 0.6V and the negative input
of comparator is already 0.6V above the sync 'floor'.
But it is not so. The capacitor C2 has almost no way to discharge and consequently it is charged
with very low current and the BE drop is about 0 V.
Therefore, the sync floor potential is equal to the voltage set by divider at the transistor base.
When the charging current rises, which happens when a new sync pulse arrives,
so does the difference between comparator inputs, so the pulse at this moment is not missed.
The circuit takes 3 pins: 2 comparator inputs and 1 output.
Comparator output could be checked by polling its configuration register,
but it takes 3 instructions to check it this way:
waitHigh mov !RB, w ;exchange comparator conwfiguration
;with w (mode = $08)
mov temp, w
jmp waitHigh ;6 cycles in loop
while it takes just 1 instruction to check the port pin
waitHigh sb RB.0
jmp waitHigh ;4 cycles in loop
So I chose to sacrifice the pin as it is better to sample the comparator output a little faster
(and smaller code size too).
Locking to the HSync frequency is the most difficult part here.
As Simon Nield suggested I use two PLL modes:
1.) Crash PLL. It is used after chip reset and when too many sync pulses are missed.
On each external pulse (longer than 2 us) SX resets RTCC and calculates error on the next pulse.
Errors are summed up for 256 samples and the timer load value is corrected
with the average error value.
The timer load value is 16 bit, higher byte adds directly to RTCC and lower one to phase accumulator.
This mode works until average error goes low enough. After that the SX enters the fine PLL mode.
2.) Fine PLL. This is the hardest part. In this mode, the RTCC load value is not corrected
(that is the line is assumed to have a fixed length), only RTCC is corrected.
The correction value is produced by a low pass filter, which averages the errors.
This works like an integral term in a PI regulator.
I found out that proportional term (subtracting current error from RTCC) doesn't help really,
because the error signal is so noisy that subtracting it from RTCC results in passing the noise further.
It works pretty well for a wide range of video sources, maybe just a bit worse than the TV circuit.
Another possible issue may be that a line can have slightly different length for a different video source. That may result in a different position of overlaid image on the screen,
because the clock is not adjusted, only its period is adjusted by PLL.
By the way, this was tested on SECAM,
but I think NTSC and PAL are very close to SECAM in the horizontal sync parameters.
In SECAM horisontal period is 64 us, sync pulse is 4.7 us, and equalizing pulses are 2.35 us.
Next step is vertical sync...
; PLL Syncronized signal over video (horizontal sync)
; SX28-52 demo board
; Crystal: 50 MHz
; RB3 - button (active low)
; RA0 - output --//---|>|--- to video
; R1 220 VD1
; RB0 - comparator output (sync active low)
; The program locks to horizontal sync pulses and outputs
; two vertical lines when the button is pressed.
; RTCC is used without prescaler as a time base. A full line
; takes 64us*50=3200 cycles or 12.5 periods (overflows) of timer.
; At the start of each line a phase variable (default is 128) is
; added to RTCC, so RTCC overflows 13 times per line.
DEVICE SX28AC, BANKS8, PAGES4
DEVICE OSCHS3, TURBO, OPTIONX
첨부된 압축파일을 내려받기 하십시요.
■ Reference : RS-170 Wave form
RS-170 Sync wave form
The color subcarrier frequency is chosen such that the black and white dots produced
by the color subcarrier appear as white and black dots in the next frame.
[ed: every second field (odds and evens) has opposite chroma polarity]
Your eye then averages these out removing the effects of the color subcarrier on b/w television receivers.
NTSC vertical sync was designed to be easily implemented on very cheap and primitive hardware,
thus, it's just a little bit funky! What happens is this.
Each frame takes up 525 lines' worth of time,
and believe it or not, each field is exactly 262.5 lines long.
The magic of vertical sync happens during nine lines' worth of time
at the top of each field, called the vertical interval.
Three lines' worth of time is spent sending six pre-equalization pulses.
Then three lines' worth of time is spent sending six actual vertical sync pulses.
Finally three lines' worth of time is spent sending *either* six or seven post-equalization pulses.
You probably already guessed that it is the second field that gets the extra post-eq pulse
and its purpose is to account for a half line offset.
Inside even the most ancient TV set is a PLL that locks to the horizontal sync pulses
in order to accomplish horizontal sync.
In order to make sure that the PLL wouldn't lose sync,
the NTSC standard guarantees that a continuous stream
of pulses shall arrive at the horizontal sync rate.
But there's half lines in there! Riiight. In order to get that to work,
the pulse rate is doubled up temporarily during the vertical interval.
In terms of horizontal sync, here's what the TV set sees. First, frame 0 begins.
There are 6 pre-eq pulses, 6 vertical synch pulses, and 6 post-eq pulses,
all at double the horizontal scan rate, taking up the first nine lines' worth of time.
Only the first and every other subsequent pulse is regarded by the PLL.
In other words, the PLL locks on to every other pulse,
at the horizontal frame rate. After those first nine lines, normal scan lines are sent,
with just one horizontal sync pulse each.
The PLL stays locked to those. At the bottom of the field, line 262 starts as usual,
but halfway through the scan line, boom!, here comes the first pre-eq pulse for field 1.
This first pre-eq pulse of field 1 is of course completely out of phase
from the other horizontal sync pulses and therefore it will be missed by the PLL.
But that's okay because the eq pulses come at double the horizontal scan rate.
So, the second and every other subsequent pulse is regarded by the PLL.
The seventh post-eq pulse brings the whole system back into sync so
that the tenth line of field 1 is consistent phase-wise with the lines in field 0.
It's really a pretty clever design for the 1930s!
[The president of the company where I work might take umbrage: he was in on the design
and certainly the engineers who participated in the birth of television were no slouches!]
For vertical sync detection, also inside the ancient TV is a simpleminded low pass filter.
The pre-eq and post-eq pulses are mostly "black" level with fleeting sync level,
so the average voltage for those three-line intervals is relatively high (close to .3v for black level).
In between there are the three lines' worth of vertical sync pulses
which are very high duty cycle into the sync voltage range, and average closer to 0 volts.
The vertical sync pulses are the only part of the entire waveform
with an average voltage anywhere near 0 volts, so they are hard to miss,
even with primitive tube circuits ;^)
While some of today's TVs ignore some of the pulses,
it is easy to generate the standard NTSC signal, and of course that is recommended.
So, to recap: Field 0 contains 262.5 lines, as follows.
3 lines: 6 pre-eq pulses
3 lines: 6 vertical sync pulses
3 lines: 6 post-eq pulses
253 lines: normal scan lines (many of these are invisible and some are reserved for closed-caption data,
cable tv scrambler data, etc... but so far as sync is concerned, these lines are all "normal" scan lines)
.5 lines: the last line of the field quits right in the middle!
Field 1 contains 252.5 lines, as follows.
3 lines: 6 pre-eq pulses
3 lines: 6 vertical sync pulses
3.5 lines: 7 post-eq pulses
253 lines: normal scan lines
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